1. Field of the Inventionxe2x80x94The present invention generally relates to the optimization of circuit designs and more particularly relates to a method and apparatus for using a placement tool to manipulate cell substitution lists.
2. Description of the Prior Artxe2x80x94Integrated circuit, printed circuit board and other related technologies are advancing at a very rapid rate. The latest generation of integrated circuits can incorporate over four times the circuitry than was possible just a few years ago. Further, circuit board and multi-chip module technology has allowed much denser circuit board designs. These and other advancements have allowed the development of increasingly complex and high speed computer systems.
The design of such computer systems has become increasingly difficult and time consuming. To maximize performance and minimize the size and power of such computer system, designers often implement much of the hardware in a number of integrated circuits. For maximum performance, the integrated circuits are often custom or semi-custom designed. Each integrated circuit may contain several hundred thousand gates, and each gate must be placed and routed in accordance with an overall computer system specification, all on a die typically measuring less than 625 mils on a side.
The overall system specification typically defines the overall function of the computer system, including the power and timing requirements thereof. Because of the size and complexity of such computer systems, system designers often partition the overall design into a number of blocks, wherein each of the blocks performs a dedicated function. Partitioning is typically continued until the size of each of the sub-blocks is of a manageable size. A specification for each of the sub-blocks is then written to define the function, timing and power requirements thereof. Often, one or more of the sub-blocks are implemented in an integrated circuit.
After the sub-block specifications have been defined, logic designers typically enter a schematic into a design database for each sub-block, using selected components from a component library. The schematic is typically entered via a schematic entry tool running on an engineering workstation, and the design database is typically stored therein.
The component library may include a number of cells wherein each of the cells implements a different function. For example, the component library may include NAND gates, NOR gates, XOR gates, registers, latches, I/O cells, etc. Further, each of the individual cells may have a logically equivalent component with a different drive strength. The desirability of having different drive strength cells within the component library is discussed in more detail below.
In addition to the above, each of the cells typically have a number of xe2x80x9crepresentationsxe2x80x9d stored in the component library. For example, a cell may have a xe2x80x9csymbolic representationxe2x80x9d, a xe2x80x9cschematic representationxe2x80x9d, and a xe2x80x9cphysical representationxe2x80x9d. When entering the schematic, the designer typically provides the xe2x80x9csymbolic representationxe2x80x9d directly on the schematic sheet via a schematic editor, and interconnects the symbols to achieve the desired function.
After the schematic has been entered into the design database, the schematic may be processed, or expanded, into a design netlist. The design netlist typically identifies each of the library cells that are used in the schematic, and further identifies the interconnections therebetween. The netlist is often written in an EDIF (Electronic Design Interface) format. EDIF is an industry wide standard, developed to allow the design netlist to be compatible with various software programs developed by different vendors.
An alternative approach for entering the design into a design database involves using sophisticated synthesis tools. The word xe2x80x9ctoolxe2x80x9d as used herein refers to a software program running on a data processing system or an application specific data processing system. In such an approach, the designer enters logical equations describing the behavior (i.e. function) of the circuit design. A first synthesis tool implements the logical equations using logical cells from the component library. A second synthesis tool may then minimize the logic using known techniques, and may attempt to optimize the design based on a number of predetermined factors. For example, the designer may direct the synthesis tool to optimize the design for speed, power, or some other factor.
Typically, the resulting design netlist is provided to a place and route tool. There are a number of place and route tools available op the market today. The place and route tool may read the xe2x80x9cphysical representationxe2x80x9d of each cell within the design and place the physical representation within an imaginary two dimensional box. For integrated circuit designs, the imaginary box often corresponds to the physical boundary of the resulting integrated circuit die.
Once all of the cells have been placed, the place and route tool interconnects the cells in accordance with the design netlist. Depending on the technology and the power bussing strategy of the component library, the place and route tool may provide the required interconnections (or routes) using up to five layers of metal.
Initially, the place and route tool may not take into account critical timing paths or other design parameters.
However, most modern place and route tools have the capability of biasing the placement and routing of the cells to favor predetermined nets within the design database.
In some cases, it is advantageous to manually place certain critical cells within the design. The manual placement of these cells is typically accomplished via a placement tool (e.g. floor-planning tool). Stand alone floorplanning tools are available. However, many place and route tools have at least a limited floor-planning or placement capability. After selected critical cells are manually placed by the designer, the remaining cells may be placed and the circuit design may be routed as described above.
The output of the place and route tools is typically a netlist in the EDIF format. In most large designs, the place and route netlist is hierarchical in nature. Thus, the place and route netlist typically only identifies the placement coordinates and orientation of each of the cells within the design, and does not contain the actual physical representation of each cell. Rather, the place and route netlist contains pointers to the physical representations stored in the component library. Thus, if a particular cell is used a number of times within the design, only one copy of the physical representation is required to be stored. The place and route netlist typically also identifies the interconnections, or routes, by the coordinates of the starting, ending, and any other points where the route changes direction. Further, the width of the route is also identified.
After the place and route netlist is generated, the designer may use an extraction tool to extract an RC file therefrom. The extraction tool may process the place and route netlist and may determine the resistance, capacitance, or any other parameters selected by the designer, for each net in the design. For example, the extraction tool may determine the capacitance of a particular net by calculating the input load capacitance for each gate connected to the net, and may further determine the capacitance between a corresponding route and, any other layer within the design, including the substrate. That is, the extraction tool may determine what layers the particular route overlaps, and may calculate the capacitance generated therebetween.
To provide accurate results, the extraction tool is often provided with technology specific parameters including oxide thicknesses between metal layers, the permittivity of each of the oxide layers, etc. These technology specific parameters are often stored in a technology file, which may be read by the extraction tool.
After the extraction tool provides an RC file for the design, the RC file and the original netlist may be provided to a timing analysis tool. The timing analysis tool processes the netlist and the RC file to determine the timing of predetermined circuit paths within the design. Part of the pre-processing performed by the timing analysis tool is to read the timing information from the component library for each of the cells used in the design. For example, the timing information stored in the component library may include parameters such as a base delay, and delay per unit of capacitance. The timing analysis tool may use the timing information, along with the RC file to determine the delay for each cell within the design. Thereafter, the timing analysis tool identifies predetermined timing paths within the design, and adds the delay for each of the cells to determine an overall path delay for each timing path. The timing analysis tool may then report all timing paths that have an overall path delay that falls outside of a predetermined timing specification.
An approach to aid the designer in evaluating and correcting the timing violations identified by the timing analysis tool is suggested in an article entitled xe2x80x9cCML III Bipolar Standard Cell Libraryxe2x80x9d, by Brian N. Tufte (Proceedings of the 1988 Bipolar Circuits Conference, Minneapolis, Minn., 1988). Tufte suggests using a software tool called SPEN (Speed Power Enhancement Program) to identify cells within the design that could be replaced by a higher power cell to reduce the delay of the corresponding timing path.
After cells have been identified for substitution, the designer may make the desired changes to the original design database. This may be accomplished by manually manipulating the design database using a database editor tool, or by manually creating a script to direct the database editor to make such changes. Alternatively, and depending on the how the database was originally entered, the designer may manually edit the original behavioral equations by substituting the selected higher power cells therein.
In either case, the design database is again expanded or synthesized to provide an updated design netlist incorporating the substituted cells, which may be provided to the place and route tool. The updated design may then be placed and routed. The, process of placing and routing the design, extracting an RC file, performing timing analysis, identifying cells for substitution, and updating the design database may be repeated until the design falls within the timing specification.
A limitation of the above design approach is that each iteration may take an unacceptable amount of time to complete. A substantial portion of the above referenced design cycle may be consumed by the expansion or synthesis of the design database, and by the placing and routing the design netlist. It would thus be advantageous to eliminate these steps from subsequent design iterations.
The present invention overcomes many of the disadvantages of the prior art by providing a floorplanning tool that may import and export cell substitution and/or cell selection lists. The cell substitution and/or cell selection lists may be used by the floorplanning tool to substitute and/or modify the placement design database, rather than the original schematic or behavioral database. This may eliminate the need to re-synthesize and re-place and route the circuit design during each design iteration. The present invention further contemplates providing a reset feature which may reset the circuit design database to a previous state, if desired.
The present invention recognizes that the placement and routing of a typical circuit design may not significantly change when only selected cell substitutions and/or minor placement changes are made therein. Thus, it is recognized that it may not be necessary to repeat the synthesis step and/or the place and route step during each design iteration, as taught by the prior art. Rather, it is contemplated that selected design changes may be made in the placement design database. The design verification steps may then be performed on the modified placement design database, thereby eliminating the need to re-synthesize and re-place and route the circuit design during each design iteration.
The import feature of the present invention may be used to read a selected cell substitution list into a placement tool. The cell substitution list may identify selected cells that may be substituted with logically equivalent cells to overcome pre-identified timing and/or physical violations. In a preferred embodiment, the cell substitution lists may be generated in accordance with U.S. patent application Ser. No. 08/598,506, filed Feb. 7, 1996 entitled xe2x80x9cMethod and Apparatus for Performing Drive Strength Adjust Optimization in a Circuit Designxe2x80x9d, U.S. patent application Ser. No. 08/597,931, filed Feb. 7, 1996 entitled xe2x80x9cMethod and Apparatus for Resolving Conflicts Between Cell Substitution Recommendations Provided by a Drive Strength Adjust Toolxe2x80x9d, and U.S. patent application Ser. No. 08/597,847, filed Feb. 7, 1996 entitled xe2x80x9cMethod and Apparatus for Performing Timing Analysis on a Circuit Designxe2x80x9d. The floorplanning tool may then substitute the selected cells identified in the cell substitution list, if desired.
The import feature may also allow a circuit designer to easily identify and correct cell placements that cause pre-identified physical violations. A cell selection list may identify selected cells that are involved in detected physical violations. In a preferred embodiment, the placement tool may import the cell selection list to identify and correct the cell placements that caused the physical violations. This is further described in U.S. patent application Ser. No. 08/789,025, filed Jan. 27, 1997, entitled xe2x80x9cMethod and Apparatus for Efficiently Viewing a Number of Selected Components Using a Database Editor Toolxe2x80x9d, U.S. patent application Ser. No. 08/789,026, filed Jan. 27, 1997, entitled xe2x80x9cMethod and Apparatus for Selecting Components Within a Circuit Design Databasexe2x80x9d, and U.S. patent application Ser. No. 08/789,024, filed Jan. 27, 1997, entitled xe2x80x9cMethod and Apparatus for Identifying Physical Errors in a Placement Databasexe2x80x9d.
The export feature of the present invention may allow the placement tool to write selected cell substitution and/or cell selection lists to a file. This may be useful if later design iterations result in changes that must be discarded, or may provide a base from which future changes can be judged. The export feature may also be used to write the entire placement design database to a file.
Finally, the present invention contemplates providing a reset feature, which may reset a circuit design database to a previous state. This may be accomplished by using a number of the previously stored cell substitution and/or cell selection lists. The resetting feature may be particularly useful when a selected previous design iteration is found to provide the best design results. The importing feature may be used to import each of the cell substitution lists for each of the design iterations subsequent to the selected iteration. Then, the resetting feature may reset the circuit design to a state that corresponds to the selected previous design iteration by simply reversing the cell substitutions indicated therein. Likewise, the resetting feature may be used to discard all cell substitutions, and return the circuit design to an original or default state.
As indicated above, the exporting feature may write the entire placement design database to a file. This may be done for each design iteration. Thus, it is contemplated that the resetting feature may reset the circuit design database to a previous state by simply reading the appropriate previous placement design database that corresponds to the desired design iteration.